Typically an integrated circuit will comprise the functional circuitry needed to perform the processing functions of the integrated circuit, along with interface circuitry (often referred to as input/output (I/O) circuitry for providing an interface between the functional circuitry and components external to the integrated circuit. Often the interface circuitry takes the form of an I/O ring surrounding the functional circuitry and incorporating all of the required I/O cells to facilitate the input/output requirements of the integrated circuit.
Typically the various I/O cells are placed side by side around the I/O ring, and incorporate a power supply line structure which extends around the I/O ring to provide the required power supplies to the I/O cells.
Whilst the functional circuitry of the integrated circuit will typically operate from a first power supply, many of the components within the interface circuitry will operate from a second power supply different to the first power supply. However, in addition, there are typically a number of interface components within the interface circuitry which need to operate from the first power supply. Accordingly, it is typically the case that the power supply line structure provided within the I/O ring needs to provide both the first power supply and the second power supply. Additionally, the power supply line structure has to be sized sufficiently to support a current carrying constraint of the interface circuitry. In particular, the I/O cells will typically include electrostatic discharge (ESD) components used to provide ESD protection during ESD events, and as a result the various lines within the power supply line structure need to be sized sufficiently to manage the relatively large currents that arise during such ESD events.
Often the various supply lines of the power supply line structure are provided within the upper metal layers (also referred to as the thick metal layers) of the integrated circuit where they can be sized appropriately to manage the current drawn during such ESD events. However, this results in the area occupied by the power supply line structure becoming relatively large, and in particular the sizing requirements of the power supply line structure are becoming a limiting constraint when seeking to reduce the size of the I/O cells.
As the size of integrated circuits continues to decrease, there is an ever increasing pressure to reduce the size of the I/O cells used to form the interface circuitry of the integrated circuit. This pressure applies not only when the interface circuitry is arranged as an I/O ring as discussed above, but also in other configurations of interface circuitry, such as in area array System-on-Chips (SoCs) where several clusters of I/O cells are distributed within the integrated circuit instead of being formed as a ring around the periphery of the chip. In all of these various arrangements, the above-mentioned current carrying constraints (typically due to ESD protection requirements) have limited the reductions that can be made in the size of the power supply line structure provided within the I/O cells, thus limiting the extent to which the area occupied by the I/O circuitry can be reduced, and hence limiting the reductions that can be made in the size of the integrated circuit.
Accordingly, it would be desirable to provide an improved arrangement for providing the necessary power supplies to the interface circuitry of an integrated circuit, whilst enabling the current carrying requirements to continue to be met.